1. Technical Field
The present disclosure relates to integrated circuit memories comprising split gate memory cells, each comprising a selection transistor section and a floating-gate transistor section. The selection transistor section comprises a selection gate and the floating-gate transistor section comprises a floating gate and a control gate.
2. Description of the Related Art
So-called “split gate” memory cells are conventionally programmed by hot-electron injection (or “hot-carrier injection”). Compared to tunnel-effect programming, programming by hot electrons has the advantage of being short, generally 100 times shorter than tunnel-effect programming. For a better understanding, the programming time of a memory cell by hot-electron injection is typically in the order of a few microseconds compared to a few milliseconds for tunnel-effect programming.
During hot-electron programming, the two transistor sections of the memory cell cooperate in order to inject electric charges into the floating gate. The selection transistor section has a conductive channel in which a current appears, which comprises high kinetic energy electrons, referred to as “hot electrons”. When this current reaches the conductive channel of the floating-gate transistor section, an injection zone appears where the high energy electrons are injected into the floating gate under the effect of a transverse electric field created by the voltage applied to the control gate.
To obtain a good injection performance, one should ensure that the selection transistor section operates in saturated mode so that its conductive channel has a pinch zone in the vicinity of the injection zone. The concentration of the current in the pinch zone favors the appearance of high kinetic energy electrons, the injection performance then being maximized. This saturated operating mode of the selection transistor section is also referred to as “weak-inversion” or “subthreshold” (operating mode below the threshold voltage).
The saturated operating mode of the selection transistor section is conventionally obtained by imposing a low programming current in the memory cell, by means of a current source, while the drain-source voltage of this transistor section adjusts automatically to the imposed current, by cascode effect. This configuration is shown in FIG. 1, which shows the arrangement of a split gate memory cell C1i,j in a word line WLi of a memory array, and the arrangement of the above-mentioned current source, designated by the reference IG1.
The selection gate SG of the selection transistor ST section of the memory cell is connected to a selection line SLi and the control gate CG of the floating-gate transistor FGT section is connected to a control gate line CGLi. The drain D of the selection transistor section is connected to a bit line BLj and the source S of the floating-gate transistor FGT section is connected to a source line SCLi. The selection SLi, control gate CGLi and source SCLi lines are parallel and linked to all the memory cells of the word line. The bit line BLj is transverse to the lines SLi, CGLi, SCLi and is also connected to memory cells belonging to other word lines (not represented).
The current source IG1 is arranged between the end of the bit line BLj and the ground. The selection line SLi receives a selection voltage VSi, the control gate line CGLi receives a gate voltage VGi and the source line SCLi receives a source line voltage VSL. Voltage VG is generally high, for example 10V, to generate in the channel of the floating-gate transistor FGT section a transverse electric field favoring the injection of electrons into the floating gate. Voltage VSL is sufficiently high, for example 4V, to ensure the conduction of the memory cell. The selection voltage VS is generally set at any value greater than the threshold voltage of the selection transistor section, for example between 1V and 3V, the saturated operating mode of the selection transistor ST section being imposed by the current source IG1. The programming current imposed by the current source IG1 thus circulates from the source line SCLi to the bit line BLj. A flow of electrons circulating in the opposite direction to the current passes through the channel of the selection transistor section until it reaches the pinch zone, and then the injection point into the channel of the floating-gate transistor section.
Offsetting their good injection performance, split gate memory cells have the disadvantage of occupying more semiconductor surface than conventional flash memory cells, that are also programmed by hot-electron injection but comprise only one control gate.
U.S. Pat. No. 5,495,441 discloses a so-called “split gate” memory cell the selection transistor section of which is arranged vertically to reduce the footprint of the memory cell. FIG. 2 corresponds to FIG. 7 of that document and shows a cross-section of the structure of such a memory cell. The numerical references in FIG. 2 are those of the original FIG. 7 of the aforementioned document. The memory cell C2 shown in FIG. 2 comprises a trench etched in a substrate (27) after forming a floating gate FG (28) made of polysilicon (polycrystalline silicon) above the substrate. The trench has then been covered with an oxide layer (200a, 200b). A conductive layer made of polysilicon (26) has then been deposited on the entire memory cell. The conductive layer (26) has a portion extending in the trench and forming a vertical selection gate SG, a portion extending over the floating gate FG (28) forming a horizontal control gate CG, the rest of the conductive layer forming a selection line SL of the memory cell. A doped region (21) implanted in the substrate forms a bit line BL and doped regions (20) implanted at the bottom of the trench form “source bit lines” SBL that are parallel to the bit line BL (21). The memory cell C2 thus comprises a selection transistor ST section having a vertical channel of length L1, and a floating-gate transistor FGT section having a horizontal channel of length L2, which cooperate to form a transistor having a channel of length L1+L2. The control CG and selection SG gates of the two transistor FGT, ST sections are formed by the same conductive layer (26) and therefore form a single component. The memory cell C2 is formed together with a memory cell C2′ linked to the same selection line SL (26) and to the same bit line BL (21), but to a different “source bit line” SBL′ (20).
As shown in FIG. 3, this structure of memory cell C2, C2′ has a memory array architecture that differs greatly from the conventional architecture shown in FIG. 1. The sources S of the selection transistor ST sections of the two twin memory cells are connected to the “source bit lines” SBL (20), SBL′ (20) that are parallel to the bit line BL (21). The selection line SL (26), and the gates SG (26) and CG (26) of the memory cells are at the same electric potential, the gates SG and CG thus forming a single selection/control gate. The programming of the memory cell C2 requires arranging the current source IG1 on the side of the selection transistor ST section, i.e., here in the “source bit line” SBL.
This memory cell structure offers a low footprint thanks to the vertical arrangement of the selection transistor section. On the other hand, it involves a multiplication of the number of source lines, in the form of “source bit lines” SBL, thus entailing a multiplication of the means for switching voltages in the memory array. For example, a word line comprising 1,024 memory cells would have 512 bit lines and 1,024 “source bit lines” parallel to the bit lines, compared to 1,024 bit lines and a single source line in a conventional architecture of the type shown in FIG. 1. Moreover, providing a single gate forming both a control gate and a selection gate does not enable the injection performance to be controlled as efficiently as with a conventional split gate memory cell of the type represented in FIG. 1.
From the prior art that has just been presented, it will be noted that the control of the programming current by means of a current source involves placing the current source in a line connected individually to a first terminal of the memory cell, i.e., a bit line BL in the memory array architecture in FIG. 1 or a “source bit line” SBL in the memory array architecture in FIG. 3, and applying to a second terminal of the memory cell the drain-source voltage or source-drain voltage of the memory cell making it conductive.
Thus, providing a selection transistor section having an embedded vertical gate involves an individualization in prior art and thus a multiplication of the source lines in the form of “source bit lines”, to individually control the programming currents applied to each memory cell.
It could thus be desirable to provide a memory cell architecture and a method of programming such a memory cell whereby it is possible to benefit from certain advantages of the known architectures without some of their drawbacks.